In hardware for performing multimedia signal processing, there may be multiple memory modules that contain the data required for multimedia signal processing operations. Because the data may be stored in more than one memory module, there are programmatic issues related to retrieving the data in a fast and efficient manner. The data required for a multimedia application may be located in more than one memory module because of the requirements for the data storage, or because of bandwidth limitations of the multimedia signal processing system.
Referring to FIG. 1, a general multimedia signal processing architecture 100 is shown, according to the prior art. An input/output module 110 forwards data to multimedia processor 120, and also receives processed data from multimedia processor 120. Multimedia processor 120 performs signal processing operations on input data and stores the results in one or more memory modules 150. The input data to multimedia processor 120 may originate from input/output module 110 or from the one or more memory modules 150. A processor/memory interface 130 handles the interactions between the one or more memory modules 150 and the multimedia processor 120. The functionality of processor/memory interface 130 can become complicated when multimedia processor 120 requires data that is stored in more than one memory module (for example memory module 135 and memory module 140). Accessing data stored in more than one memory module can increase the coding required in processor/memory interface 130, and can increase application complexity.
An example of a system that stores data in multiple memory modules due to bandwidth limitations is a motion estimating unit in a video encoding application. In this application, pixel data have to be stored in multiple memory modules in order to increase the bandwidth of the data transferred to the motion estimation unit. In this example, as well as other applications, it is desirable to achieve multiple memory accesses per clock cycle. This design consideration impacts the design of the interface between the multimedia processing and the memory modules since coding efficiency is related to the number of parallel memory fetches that can occur within a single clock cycle.
A programmatic approach that abstracts the interface to a plurality of memory modules so that multiple memory modules which may contain heterogeneous data could be accessed by reusing the same section of code would be advantageous. It would also be advantageous if this section of code could be executed within a single clock cycle, and would further remove the physical addresses of the plurality of memory modules from the multimedia processor. A common approach to abstracting the plurality of physical addresses is to use a virtual address translation application that is part of the processor/memory interface. Virtual address translation allows the multimedia processor to represent the plurality of memory modules using a convenient representation which is translated to the physical addresses of the data contained in memory as necessary.